1. Field of the Invention
The present invention relates to a leadframe for semiconductor packages, as well as a combination of a top mold and the leadframe. Further, the present invention relates to a mold for molding the semiconductor package. More particularly, but not by way of limitation, the present invention relates to a leadframe that reduces occurrences of chip-out and floating of a chip paddle upon singulation after encapsulation, and a mold for molding the same.
2. History of Related Art
It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal leadframes for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the leadframe are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.
As set forth above, the semiconductor package therein described incorporates a leadframe as the central supporting structure of such a package. A portion of the leadframe completely surrounded by the plastic encapsulant is internal to the package. Portions of the leadframe extend internally from the package and are then used to connect the package externally. More information relative to leadframe technology may be found in Chapter 8 of the book Micro Electronics Packaging Handbook, (1989), edited. by R. Tummala and E. Rymaszewski. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y., which is hereby incorporated by reference.
Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, consumer demand increases. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1xc3x971 mm to 10xc3x9710 mm. Examples of such semiconductor packages are referred to as MLF (micro leadframe) type semiconductor packages and MLP (micro leadframe package) type semiconductor packages. Both MLF type semiconductor packages and MLF type semiconductor packages are generally manufactured in the same manner.
A typical leadframe used in a semiconductor package is comprised of a plate-type metal frame body that is provided with and a tie bar, which is internally extended from each of the four corners. A chip paddle is in contact with the tie bars. A semiconductor chip is mounted on the chip paddle. A plurality of leads are located along and at a distance away from the perimeter of the chip paddle. From the internal leads external leads are extended with their terminals being connected to the frame body. Dam bars 10 are provided between the internal leads and the external leads to prevent a molding material from flowing over the external leads upon encapsulating. The dam bars, the external leads, and predetermined areas of the tie bars and the frame body are all removed in a subsequent singulation process.
After a semiconductor chip is mounted on the chip paddle, the leadframe is positioned between a top mold and a bottom mold and encapsulated by a molding material.
The top mold is designed to clamp the dam bar of the leadframe and a part of the internal leads located at the internal side of the dam bar with the aid of a sill and to provide a cavity on the internal side of the sill in which the semiconductor chip, etc. are encapsulated with the encapsulation material. At one side of the cavity, a mold gate is formed as a passage through which the encapsulation material flows. To discharge the air, gas and dregs of the encapsulation material, (hereinafter referred to as flash), to the outside in the molding process, a plurality of air vents are also provided.
The mold gate is formed to have a space between the tie bar of the leadframe and the upper surface of the body. Because the four corner areas of the leadframe (in which the tie bars are formed) are not clamped by the sill of the top mold and because the mold gate is connected to the cavity, the molding material flows along the upper surface of the leadframe, the upper surface and opposite end sides of the tie bars and the mold gate into the inside of the cavity. Herein, the upper surface of the tie bar and its opposite end sides in the leadframe, with which the molding material is in contact while flowing into the cavity, is defined as a frame gate.
In addition, a mold air vent formed in the top mold is connected to the cavity, so that the molding material flash, gas and air are discharged along the surface of the leadframe, the upper surface and opposite end sides of the tie bar and the mold air vent to the outside in the molding process. Herein, the upper surface of the tie bar and its opposite end sides in the leadframe, with which the flash is in contact while flowing into the cavity, is defined as a mold air vent.
After completion of the encapsulation, a molding material flash is usually formed at the side of the package body. That is, a significant amount of the flash is formed at positions corresponding to the mold gate of the top mold and to the mold air vent, respectively. In addition, the flash is connected to the package body formed inside the cavity. Some flash is removed when the leadframe is ejected from the top mold and the bottom mold.
The flash is not uniform in thickness owing to various factors such as molding pressure, molding period of time, temperature, etc. and, therefore causes problems in the singulation of the leadframe.
The encapsulated semiconductor package is preferably firmly positioned between a bottom clamp and an upper clamp while turning upside down. Thereafter, a boundary area between the internal leads, the dam bars and a predetermined area of the tie bars are cut with the aid of a singulation tool. At this time, any flash present on the tie bars of the leadframe prevents close contact of the semiconductor package with the bottom clamp.
After the singulation tool is allowed to descend, different stresses are generated at the square corners of the semiconductor package, which may result in cracking a part of the package body and even causing a chip-out phenomenon. Once a chip-out occurs, the semiconductor package, even though able to function normally, has a reduced commercial value and thus, is less marketable. Where a serious chip-out phenomenon occurs, wires that connect the semiconductor chip and the internal leads may be cut or the semiconductor chip may be exposed to the outside of the package body.
Because the sill of the top mold clamps only the internal leads and the dam bars during the encapsulation, the pressure of the molding material causes the chip paddle to lean on one side or float, giving rise to an increase in wire sweeping in addition to leaving a significant amount of flash on the bottom surface of the chip paddle. In an MLF package, typically, the internal leads and the chip paddle are externally exposed at their bottom surfaces. Thus, when a flash is formed on the chip paddle, it must be removed or the semiconductor package is regarded defective.
The present invention relates to leadframes for semiconductor packages. More particularly, one aspect of the present invention comprises a semiconductor package, including a frame body and a chip paddle that is defined by inner voids that are formed in the frame body. The leadframe has at least one tie bar that communicates with an outer portion of the frame body with the chip paddle and at least one dam bar in communication with an outer surface of the inner void. In the embodiment presented, at least one end of an inner void extends outwardly beyond the dam bar to provide a flow under pathway for the encapsulating material when the leadframe is engaged by a top mold.
In the above described embodiment of the present invention, the top mold comprises a sill that protrudes from a face of a base plate. The sill defines a cavity and has a contact surface on a distal end of the sill. The sill in continuous such that the cavity is completely enclosed when the contact surface is mated against a flat surface. When the contact surface of the sill engages the leadframe, the sill clamps onto the die bar of the leadframe. In another embodiment, the sill is wider such that the sill engages the dam bar, a plurality of inner leads and a plurality of outer leads of a leadframe when the upper mold engages the leadframe.
The semiconductor chip assembled in accordance with the various embodiments of the present invention is also encapsulated to form a semiconductor package by locating a semiconductor chip on a chip paddle of a leadframe. The leadframe is clamped by the sill of a top mold. Encapsulating material is flowed into a mold gate of the leadframe and under a portion of the sill to engulf the semiconductor chip within the cavity formed by the top mold and the leadframe.